The present invention relates to a static type RAM (Random Access Memory), and more particularly to an effective technology to be utilized in an ECL (Emitter Coupled Logic) interface by the external clock control.
A conventional ECLRAM controlled by external clock pulse takes a chip select signal CS, an address signal Ai, a write control signal WE and an input data Di in response to the rise of the clock pulse, and starts the write operation. While the clock pulse is at high level, the output is latched and data at the previous cycle remains to be held. If the clock pulse is varied to low level, the latch of the output buffer is released and new state is outputted to the outside.
In such conventional ECLRAM, if a signal latched at the rise of the above-mentioned clock pulse, such as address signal, can be held only during a definite period before and after the rise of the clock pulse, it is not caught by the state in the time other than the above-mentioned definite period. Thereby even if the variation of the input signal is subjected to time fluctuation, such problem does not occur that access of the memory operation be determined. FIG. 8 shows an example of a timing diagram of the write operation.
Such ECLRAM with a control circuit is exemplified in "Fujitsu semiconductor device data sheet (MBM10476RL)", '89, pp. 871-887.
In the clock control ECLRAM as above described, problems of determination of the operation speed due to the time shift such as skew of an address signal and the erroneous writing are removed. However, it has been made clear by the studying of the present inventors that the clock control ECLRAM has new problems as follows. That is, as a first problem, data held by latch during the write operation are always outputted. Consequently, the I/O common to connect a data input terminal and a data output terminal to the common data bus cannot be adopted. Thereby at installation to a package board such as print board, a bus for data input and a bus for data output are required.
As a second problem, input data are latched in so relatively early timing as that of the address signal. Therefore in a system device such as a processor for transmitting/receiving data to and from a memory, since data are transmitted to the memory early at the beginning of the cycle and received from the memory late at the end of the cycle, it follows that use of the system device is quite difficult. At the worst case, one dummy cycle unnecessary for transmitting/receiving the data to and from the memory must be performed thereby the above-mentioned high speed property cannot be fully utilized.
As a third problem, since the ECL circuit is used, the consumption power becomes relatively large.